The ADSP - 2105 incorporates computational units, data address generators and a program sequencer in one device, utilizing external data and program memories. The ADSP-2105 contains three full-function and independent computational units: an arithmetic / logic unit, a multiplier / accumulator and a barrel shifter. The computational units process 16-bit data directly and provide for multiprecision computation. The sequencer supports single-cycle conditional branching and executes program loops with zero overhead.
The ADSP-2105 assembly language uses an algebraic syntax for ease of coding and readability.
Summary of ADSP-2105 Key Features:
· Separate Program and Data Buses, Extended Off-Chip.
· Single-Cycle Direct Access to 16K X 16 of Data memory.
· Single-Cycle Direct Access to 16K X 24 ( Expandable to 32KX24 ) of Program Memory.
· Dual Purpose Program Memory for Both Instruction and Data Storage.
· Three Independent Computational Units :
· Arithmetic/Logic Unit (ALU)
· Multiplier/Accumulator (MAC)
· Barrel Shifter
· Two Independent Data Address Generators.
· Powerful Program Sequencer.
· Single-cycle Instruction Execution.
· Multifunction Instructions.
· Four External Interrupts.
· 100 nano sec Cycle Time.
· Low Power Standby Mode.
· Arithmetic / logic unit.
· Multiplier / accumulator.
· Barrel shifter.
· Two data address generators.
· Program Sequencer.
· PMD-DMD bus exchange.
These components are supported by five internal buses:
· Program Memory Address (PMA) bus.
· Program Memory Data ( PMD) bus.
· Data memory Address (DMA) bus.
· Data Memory Data (DMD)bus.
· Result (R) bus ( Which interconnects the Computational units)
The program memory data ( PMD ) bus serves
primarily to transfer instructions from off-chip
memory to the internal instruction register. The
instruction register introduces a single level
of pipelining in the program flow. The next instruction
address is generated by the program
sequencer. This address is output onto the program
memory address ( PMA ) bus. The program sequencer minimizes
program flow overhead. The program memory address ( PMA
) bus is 14 bits wide allowing
direct access of upto 16K words of instruction code and
16 K words of data. The data memory address ( DMA )
bus is 14 bits wide allowing direct access of up to 16 K words of
data. The data memory address comes from two sources: an
absolute value specified in the instruction code (
direct addressing ) or the
output of a data address generator
( indirect addressing ).
The ADSP 2105 contains three computational blocks: an arithmetic / logic unit ( ALU ), a multiplier / accumulator ( MAC ) and a barrel shifter. Each unit functions independently of the others. All computational units contain a set of dedicated input and output registers. The registers act as a stopover point for data between the external memory and the computational circuitry, effectively introducing one pipeline level on input and one level on output. For a wide variety of calculations, it is desirable to fetch two operands at the same time; one from data memory and one from program memory.
There are two data address generators ( DAG’s ) which operate independently. Having two independent address generators allows simultaneous access of data stored in program memory and in data memory for executing dual operand instructions in a single cycle. (DAG1) can supply addresses to the data memory only, but ( DAG2) can supply addresses to either the data memory or the program memory.
With its multiple bus structure, the ADSP-2105 can fetch an instruction, compute the next instruction address, perform one or two data transfers, update one or two data address pointers and perform a computation. All instructions execute in a single cycle.
ARITHMETIC / LOGIC UNIT ( ALU
The Arithmetic / Logic Unit ( ALU ) provides a standard set of arithmetic and logical functions. The arithmetic functions are add, subtract, negate, increment, decrement and absolute value. These are supplemented by two division primitives with which multiple cycle division can be constructed. The logic functions are AND, OR, XOR (exclusive Or) and NOT.
The ALU is 16 bits wide with two 16-bits input ports, X and Y, and one output port R. The ALU accepts a carry-in-signal ( CI ) which is the carry bit from the processor. The ALU generates six status signal: the zero ( AZ ) status, the negative ( AN ) status, the carry ( AC ) status, the overflow ( AV ) status, the X-input sign ( AS ) status, and the quotient ( AQ ) status. All arithmetic status signals are latched into the arithmetic status register ( ASTAT ) at the end of the cycle. The X- input port of the ALU can accept data from two sources: the AX register file or the result ( R ) bus. The Y input port of the ALU can also accept data from two sources: the AY register file and the ALU feedback ( AF ) register. AY0 and AYI are readable and writable from the DMD bus and writable from the PMD bus. The output of the ALU is loaded into either the ALU feedback ( AF ) register or the ALU result ( AR ) register. The ALU section contains a duplicate bank of register. There are actually two AR and AF registers and two sets of AX and AY register files. Only one bank is accessible at a time .The additional bank of registers can be activated during an interrupt service routine for extremely fast context switching. The selection of the primary or alternate bank of registers is controlled by a bit in the processor mode status register ( MSTAT ). Multiprecision operations are supported in the ALU. The ALU section supports division. The division can be either signed or unsigned however, the dividend and divisor must both be of the same type.
The ALU status bits in the ASTAT register are defined below:
Flag Name Definition
AZ Zero Logical NOR of all the bits in the ALU result
register. True if ALU output equals zero.
AN Negative Sign bit of ALU result. True if ALU output is
AV Overflow Exclusive OR of the carry outputs of the two most significant address stages. True if the ALU
AC Carry Carry output from the most significant adder
AS Sign Sign bit of ALU ‘X’input. Affected only by ABS
AQ Quotient Quotient bit generated only by DIVS & DIVQ
MULTIPLIER / ACCUMULATOR ( MAC
The Multiplier / accumulator ( MAC ) provides high-speed multiplication, multiplication with cumulative addition, multiplication with cumulative subtraction and clear-to-zero functions.
MAC Block Diagram :
The multiplier has two 16 bit input ports X and Y and a 32-bit product output port P. The 32-bit product is passed to a 40-bit adder / subtractor which adds or subtracts the new product from the content of the multiplier result ( MR ) register . The MR register is 40-bits wide. The register actually consists of three smaller registers: MR0 and MR1 which are 16-bits wide and MR2 which is 8-bits wide to allow for intermediate overflow in a series of multiply/accumulate operations.
The X input port can accept data from either the MX register file or from any register on the Result ( R ) bus. The Y input port can accept data from either the MY register file or the MF register. All of the registers surrounding the MAC have the capability of being read and written in the same cycle.
The MAC section contains a duplicate bank of register. There are actually two MR and MF registers and two sets of MX and MY register files. Only one bank is accessible at a time. The additional bank of registers can be activated during and interrupt service routine for extremely fast context switching. The selection of the primary or alternate bank of registers is controlled by a bit in the processor mode status register ( MSTAT ) .Toggling this bit switches back and forth between the two register banks.
To facilitate multiprecision multiplication’s, the multiplier accepts X and Y inputs represented in any combination of signed two’s complement format and unsigned format.
X input Y
Signed X signed
Unsigned X signed
Signed X unsigned
Unsigned X unsigned
The input formats are dynamically selectable each time the multiplier is used. Saturation in the MAC is an instruction rather than a mode as in the ALU. The accumulator has the capability for rounding the 40-bit result R at the boundary between bit 15 and bit 16. Rounding can be specified as part of the instruction code. The rounded output is directed to either MR or MF . The accumulator uses an unbiased rounding scheme.
The shifter unit provides a complete set of shifting functions for 16-bit inputs, yielding a 16-bit or 32-bit output. These include arithmetic shift, logical shift, normalization, derivation of common exponent and derivation of exponent for an entire block of numbers.
The shifter section can be divided into the following components: the shifter array, the OR / PASS logic, the exponent detector, and the exponent compare logic. Barrel shifter accepts a 16-bit input and can place it any where in the 32-bit output field. The SE register is 8-bits wide and holds the exponent during the normalize and denormalize operations. The SI , SE and SR registers can be read and written in the same cycle. When this happens, the value read from the register will be the old one. The new value will be loaded into the register at the end of the cycle and therefore cannot be read out until the next cycle.. There are actually two SE,SB,SI,SR1 and SR0 registers. Only one bank is accessible at a time. The additional bank of registers can be activated during an interrupt service routine for extremely fast context switching. The selection of the primary or alternate bank of registers is controlled by a bit in the processor mode status register ( MSTAT ). The shifting of the input is determined by a control code ( C ) and a HI / LO reference signal. The HI / LO signal determines the reference point for the shifting . In the HI state all shifts are referenced to SR1 and in the LO state all shifts are referenced to SR0 . The OR / PASS logic allows the shifted section of a multiprecision number to be combined into a single quantity. When PASS is selected, the shifted array output is passed through and loaded into the shifter result ( SR ) register unmodified. When OR is selected, the shifter array is bit wise OR’ed with the current contents of the SR register before being loaded there.
The shifter performs the following functions :
· Arithmetic Shift ( ASHIFT )
· Logical shift ( LSHIFT )
· Normalize ( NORM )
· Derive Exponent ( EXP )
· Block Exponent Adjust ( EXPADJ )
DATA ADDRESS GENERATORS ( DAGs
The ADSP-2105 contains two independent data address generators ( DAGs ) so that both program and data memories can be accessed simultaneously. Both perform automatic address modification. DAG1 can only generate data memory addresses, but provides an optional bit-reversal capability. DAG2 can generate both data memory and program memory addresses, but has no bit-reversal capability.
There are three register files: the modify ( M ) register file, the indirect ( I ) register files and the length ( L ) register files. Each or the register files contains four 14-bit registers which can be read from and written to via the DMD bus. The address generators support both linear addressing and circular addressing. For linear addressing, the modified I register value is simply the sum of the M Register content and the I register content. For circular buffer addressing, if the sum of the M register content and the I register content would cross the buffer boundary, the modified I register value must be wrapped around. All data address generator register ( I,M and L registers ) are loadable and readable from the lower 14-bits of the DMD bus.
PROGRAM SEQUENCER &
The program sequencer generates a stream of instruction addresses, providing flexible control of program flow. It provides for zero overhead looping single cycle branching ( both conditional and unconditional ) and sophisticated interrupt processing. ADSP - 2105 instruction set includes the following instructions:
· RETURN FROM SUBROUTINE ( RTS )
· RETURN FROM INTERRUPT ( RTI )
· DO UNTIL
The sequencing logic controls the flow of ADSP-2105 program execution
by outputting a program memory address onto the PMA bus from one of the following four possible sources.
· PC incrementer
· PC stack
· Instruction register
· Interrupt controller
The PC incrementer is selected as the source of the next program memory address if program flow is sequential. The PC stack is used as the source for the next program memory address when a return from subroutine or return from interrupt is executed. The instruction register is selected by the next address multiplexer when a direct jump is taken. The interrupt controller provides the next program memory address when processing an external interrupt request. Data address generator 2 sources the next program memory address when executing a register indirect jump.
Down Counter and
The down counter and associated count stack provide the program sequencer with a very powerful looping mechanism. The down counter is a 14-bit register with auto decrement capability that is intended for controlling the flow of program loops which execute a predetermined number of times. The count stock is a 14-bit by 4-word stack which allows the nesting of loops by storing temporarily dormant loop counts.
Loop Comparator and
The DO UNTIL instruction executes a Zero-overhead loop using the loop compatator and loop stack. The loop comparator continuously compares the address of the last instruction in the loop ( Coded in the DO UNTIL instruction ) against the next address. When the last instruction in the loop is executed the processor conditionally jumps to the beginning of the loop eliminating the branching overhead. The loop stack stores the end addresses and termination conditions of temporarily dormant loops. Upto four levels can be stored. The only "extra" cycle associated with the nesting of DO UNTIL loops is the execution of the DO UNTIL instruction itself.
Interrupt Controller :
The interrupt controller of the ADSP-2105 allows the processor to respond to one of four external interrupts within two cycles. Because of the efficient stack and program sequencer there is no additional latency when processing unmasked interrupts. Nesting of interrupts allows higher-priority interrupts to interrupt any lower-priority interrupt service routines that may currently be executing also with additional latency. The secondary data register set, selected by MODE CONTROL instruction allows the contents of the primary data register set to be saved while a "fresh" set of registers may be switched in for use by the interrupts service routine.
There are two configuration parameters for interrupts: edge or level sensitivity and masked or unmasked operation. The four external interrupt inputs can be individually configured as either edge or level sensitive. If an interrupt input is edge-sensitive, the interrupt is recognized when two successive samples of the input reveal a high-to-low transition. Detection of this transition sets an internal latch corresponding to the active interrupt request. Edge-sensitive inputs generally require less external hardware than level-sensitive inputs. A level-sensitive interrupt must remain asserted until the interrupt is serviced. The interrupting device must then remove the interrupt request so that this interrupt is not serviced again. The automatic masking of interrupts occurs within the interrupt mask ( IMASK ) register.
Status Registers And
The status and mode bits of the ADSP-2105 are maintained internally within five registers, independently readable over the DMD and four of which can be written to from the DMD bus.
· ASTAT Arithmetic status register
· SSTAT Stack status register ( read-only )
· IMASK Interrupt mask register
· ICNTL Interrupt control register
Arithmetic Status Register ( ASTAT ) :
ASTAT is 8 bits wide and holds the status information generated by the computational sections of the processor.
· Bit 0 AZ ALU result zero
· Bit 1 AN ALU result negative
· Bit 2 AV ALU overflow
· Bit 3 AC ALU carry
· Bit 4 AS ALU X input sign
· Bit 5 AQ ALU quotient flag
· Bit 6 MV MV MAC overflow
· Bit 7 SS Shifter input sign
The bits are all positive sense. Each bit is affected only by a subset of arithmetic operations, as defined by the following table.
· AZ,AN,AV,AC Any ALU operation except DIVS,DIVQ
· AS ALU absolute value operation (ABS)
· AQ ALU divide operation (DIVS, AIVQ)
· MV Any MAC operation except saturate MR
· SS Shifter EXP operation
STACK STATUS REGISTER ( SSTAT
SSTAT is 8-bit wide and holds information regarding the four internal stacks. The bit in SSTAT are defined as follows:
· Bit 0 PC stack Empty
· Bit 1 PC stack overflow
· Bit 2 Count stack Empty
· Bit 3 Count Stack Overflow
· Bit 4 Status Stack Empty
· Bit 5 Status Stack Overflow
· Bit 6 Loop Stack Empty
· Bit 7 Loop stack Overflow
All of the bits are positive sense. The empty status indicate that the number of pop operations for the stack is greater than or equal to the number of push operation since that last reset. The overflow status bits indicate that the number of push operations for the stack has exceeded the number of pop operation by an amount that is greater than the depth of the stack. Since SSTAT is a read-only register, write operations will have no effect on the stack status bits either. A processor reset must be executed to clear the stack overflow status.
MODE STATUS REGISTER (
MSTAT ) :
MSTAT is a 4-bit register that defines various operating modes of the processor. The bits in MSTAT are defined as follows:
· Bit 0 Data Register Bank select
· Bit 1 Bit Reverse Mode ( Data Address Generator 1 Only )
· Bit 2 ALU Overflow Latch Mode
· Bit 3 AR Saturation Mode
All registers can be changed by moving a new value into them with any of the MOVE instructions. In contrast to the other status registers, MSTAT can also be changed with the MODE CONTROL instruction. The bit-reverse mode, when enabled, bit wise reverses all addresses generated by data address generator one ( DAG1 ).
Interrupt Mask Register ( IMASK ) :
IMASK is a 4-bit register which enables and disables the individual interrupt levels. The bits in IMASK are defined as follows:
· Bit 0 IRQ0 Enable
· Bit 1 IRQ1 Enable
· Bit 2 IRQ2 Enable
· Bit 3 IRQ3 Enable
The bits are all positive sense. IMASK is set to zero upon a processor reset or when an interrupt is processed with the interrupt nesting mode bit set to zero.
INTERRUPT CONTROL REGISTER (
ICNTL ) :
ICNTL is a 5-bit register that configures the interrupt modes of the processor. The bits in ICNTL are defined as follows.
· Bit 0 IRQ0 Sensitivity
· Bit 1 IRQ1 Sensitivity
· Bit 2 IRQ2 Sensitivity
· Bit 3 IRQ3 Sensitivity
· Bit 4 interrupt Nesting Mode
The IRQ sensitivity bits determine whether a given interrupt input is edge- or level-sensitive. These bits are all undefined after a processor reset.